Integrated circuit having complementary heterojunction field effect transistors

ABSTRACT

The circuit comprises a heterojunction formed between a layer (6) comprising an III-V semiconductor material having a wide forbidden band and a layer (5) comprising an III-V semiconductor material having a narrow forbidden band and whose crystal lattice mismatch with the remainder of the structure is such that the layer comprising the narrow forbidden band material is under uniaxial compression strain in the plane of the layer. 
     According to the invention the thickness of the layer (6) comprising the wide forbidden band material is selected to be smaller for the p-channel transistor than for the n-channel transistor, the ratio of these respective thicknesses being a predetermined ratio that is a function of the relative tunnel transparency for holes compared with that for electrons.

The invention relates to integrated circuits having complementaryp-channel and n-channel field effect transistors.

Integrated circuits using complementary AlGaAs/GaAs heterojunctiontransistors (also called HIGFETs for "Heterojunction Insulated-GateField-Effect Transistors") are described by D .E. Grider et al. inDelta-Doped Complementary Heterostructure FETs with High Y-ValuePseudomorphic In_(y) Ga_(1-y) As Channels for Ultra-Low Power Digital ICApplications, IEDM Digest 1991, p. 235. In their work, D. E. Grider etal. have made 4-Kbit static random access memories (SRAM) having lowelectrical power consumption. More recently, they have improved theirtechnology so as to further reduce the electrical power consumption oftheir integrated circuit (G. S. LaRue and D. E. Grider, ComplementaryHFET 32-bit Serial Multiplier, GaAs IC Symposium 92 Digest, p. 89).

The invention relates to that type of AlGaAs/GaInAs heterojunction typeof component, and it seeks to mitigate a certain number of imperfectionsand limitations (explained in greater detail below) of known componentsthat have already been proposed.

More precisely, an object of the present invention is to propose asuitable choice of thicknesses and of compositions for the epitaxiallayers of such structures enabling complementary circuits to beimplemented having very low electrical power consumption, whilesimultaneously increasing the transconductance of the p-channeltransistor. That has not been possible until now because although animprovement in circuit power consumption has been achieved, there hasbeen no improvement in the transconductance of the p-channel transistor.The reasons for these improvements are explained in detail below.

To this end, the component of the invention which is of the typecomprising an integrated circuit having complementary components of thep-channel and n-channel field effect transistor type, with aheterojunction formed between a layer comprising an III-V semiconductormaterial having a wide forbidden band and a layer comprising an III-Vsemiconductor material having a narrow forbidden band and whose crystallattice mismatch with the remainder of the structure is such that thelayer comprising the narrow forbidden band material is under uniaxialcompression strain in the plane of the layer, is characterized in thatthe thickness of the layer comprising the wide forbidden band materialis selected to be smaller for the p-channel transistor than for then-channel transistor, the ratio of these respective thicknesses being apredetermined ratio that is a function of the tunneling probability forholes compared with that for electrons.

In a first aspect of the invention, the heterojunction defines a quantumwell including HH and LH type sub-bands in the valence band diagram ofthe heterostructure in the level that comprises the narrow forbiddenband material, and the composition of the narrow forbidden band materialis selected so that the energy differences between the sub-bands HH₁,HH₂ and LH₁ is such that the population of the LH₁ sub-band isessentially negligible and the gate leakage current of the p-channeltransistor is essentially dependent of the low tunnel probability heavyholes HH₁ and HH₂.

In a second aspect of the invention, the thickness of the layercomprising the wide forbidden band material that is selected to bethinner for the p-channel transistor than for the n-channel transistoris further selected to as to reduce the absolute values of the thresholdvoltages of said transistors, thereby reducing the electrical powerconsumption of the circuit while increasing the transconductance of thep-channel transistor.

According to various advantageous characteristics or embodiments:

The material having a wide forbidden band is Al_(x) Ga_(1-x) As or(Al_(x) Ga_(1-x))_(u) In_(1-u) P and the material having the narrowforbidden band is Ga_(y) In_(1-y) As, said materials being grownepitaxially on a GaAs substrate.

The material having a wide forbidden band is Al_(z) In_(1-z) As or InPand the material having a narrow forbidden band is Ga_(y) In_(1-y) As,said materials being grown epitaxially on an InP substrate.

The layer comprising the wide forbidden band material includes anepitaxial stack comprising: a first elementary layer comprising the wideforbidden band material; an optional second elementary layer, differentin composition from the first elementary layer, and suitable forfacilitating selective etching thereof; and a third elementary layercomprising the wide forbidden band material; the thicknesses of thefirst and third elementary layers are selected in such a manner that theratio of the thickness of the first elementary layer to the totalthickness of the first and third elementary layers is equal to saidpredetermined ratio; and the gate of the p-channel transistor isdisposed in such a manner as to provide contact with the secondelementary layer.

Under such circumstances, and in the context of the above-mentionedsecond aspect, the threshold voltages of the transistor, in absolutevalue terms, may be less than 0.5 V, and the transconductance of thep-channel transistor may be improved by a factor of more than 1.25relative to that of a p-channel having its gate deposited on the layercomprising the material having a wide forbidden band.

In which case, the composition of the first elementary layer is selectedto be different from the composition of the third elementary layer insuch a manner that the potential barrier ΔE_(v) corresponding to thediscontinuity in the valence band between the materials of the firstelementary layer and of the layer comprising the narrow forbidden bandmaterial and which determines the tunneling probability for holes, isselected independently of the potential barrier ΔE_(c) corresponding tothe conduction band discontinuity between the materials of the thirdelementary layer and of the layer comprising the narrow forbidden bandmaterial and which determines tunneling probability for electrons,thereby reducing the thickness of the first elementary layer andconsequently reducing the threshold voltages of the transistors tovalues of less than about 0.4 V, and increasing the transconductance ofthe p-channel transistor relative to the case where the first and thirdelementary layers are identical.

The following preferred choices of materials may then be implemented,with the material being grown in each case by epitaxy on a GaAssubstrate: first elementary layer in AlAs and third elementary layer ofAl_(x) Ga_(1-x) As, with 0 5≦x_(Al) ≦0.75; first elementary layer ofAlAs and third elementary layer of Al_(u) In_(1-u) P with u_(Al) ≈0.50;first elementary layer of Al_(u) In_(1-u) P with u_(Al) ≈0.50 and thirdelementary layer of Al_(x) Ga_(1-x) As with 0.5≦x_(Al) ≦0.75; firstelementary layer of Al_(u) In_(1-u) P with u_(Al) ≈0.50 and thirdelementary layer of GaP_(s) Sb_(1-s) with s_(P) ≈0.65; and withepitaxial growth on a substrate of InP: first elementary layer of InPand third elementary layer of Al_(z) In_(1-z) As, with z_(Al) ≈0.48;first elementary layer of InP and third elementary layer of GaP_(s')Sb_(1-s'), with s'_(P) =0.35.

The second elementary layer may be absent and the selectivity ofselective etching of the first elementary layer is then ensured by thedifference in chemical composition between the first elementary layerand the third elementary layer.

The doping is doping that is not uniform over the entire circuit, saiddoping being obtained by impurities that are locally implanted in then-channel and in the p-channel transistors at different implantationconcentrations, with the concentration that corresponds to p-channeltransistors being optionally equal to zero.

An additional layer is interposed between the buffer layer and the layercomprising the narrow forbidden band material, the material of theadditional layer presenting, relative to the layer comprising the narrowforbidden band material, a valence band discontinuity that is not lessthan about 100 meV.

The invention is described in detail below with reference to theaccompanying figures; it will be observed that in all the figures thesame references always designate identical elements.

FIG. 1 shows the general starting structure of the invention having twotransistors, respectively an n-channel transistor and a p-channeltransistor.

FIGS. 2a, 2b, and 2c show the appearance of the conduction band and ofthe valence band for the structure of FIG. 1, respectively while atrest, while a positive gate voltage is being applied to the n-channeltransistor, and while a negative gate voltage is being applied to thep-channel transistor.

FIG. 3 is a plot of energy as a function of wave vector showing thevalence band of GaAs and of GaInAs for a material that is not understrain.

FIG. 4 is a diagram of the structure of a strained heterojunction and itshows the nature of the strains to which it is subject.

FIG. 5 is analogous to FIG. 3 but applicable to the strained material ofFIG. 4.

FIGS. 6a and 6b how the appearance of the valence band respectively atrest and while a negative gate voltage is being applied for a strainedAl_(x) Ga_(1-x) As/Ga_(y) In_(1-y) As/Al_(x) Ga_(1-x) As structure ofthe type shown in FIG. 4.

FIGS. 7a and 7b are similar to FIGS. 6a and 6b for a non-symmetricalquantum well corresponding to a strained Al_(x) Ga_(1-x) As/Ga_(y)In_(1-y) As/GaAs structure.

FIG. 8 shows the stack of layers enabling a component of the inventionto be made, while in its initial state prior to being etched.

FIG. 9 shows the same structure after etching, with a pair ofcomplementary n-channel and p-channel transistors.

FIG. 1 is a diagram showing the basic structure which is known per seand from which the invention is derived. This structure comprises insuccession:

a substrate 1 of GaAs;

a buffer layer 2, likewise of GaAs or else constituted by a GaAs/AlGaAsstack, but having thoroughly controlled crystallographic and chemical(purity) characteristics, extending over a thickness of 500 nm (withthis thickness value like all the others that follow constituting atypical value given solely as an indication, unless specifiedotherwise);

bulk or planar silicon doping 3 ("δ-doping");

a layer 4 of GaAs having a thickness of about 3 nm;

a layer 5 of Ga_(y) In_(1-y) As, that is 4 nm to 15 nm thick, and thathas a gallium content Y_(Ga) of the order of about 0.75 to about 0.80(here, as below, all contents are given in terms of molar fractions);

a layer 6 of Al_(x) Ga_(1-x) As that is 25 nm thick, and that has analuminum content x_(Al) of the order of about 0.75; and

a protective layer 7 of GaAs, that is 3 nm thick.

Incidentally, it will be observed that III-V alloys other than thosespecified can be used, for example a layer 6 of Ga_(u) In_(1-u) P or of(Al, Ga) In_(1-u) P having a crystal lattice constant that is matched toGaAs, or else Al_(z) In_(1-z) As on a layer 5 of GaInAs having a crystallattice constant matched to InP.

In addition, except for the doping 3, all of the layers forming thisstarting structure are non-doped layers.

n-channel and p-channel field effect transistors can be formed on thisstructure by implanting respective nHu +and p⁺ zones of dopingreferenced 8 and 9 that penetrate down to the layer 3, and by formingsource, drain, and gate electrodes S, D, and G on the surface in amanner that is entirely conventional.

It is thus possible to make logic circuits that have complementaryn-channel and p-channel transistors. For an n-channel transistor, if ahighly positive voltage is applied to its gate, i.e. a voltage greaterthan a threshold V_(Tn), then electrons will accumulate in the layer 5of Ga_(y) In_(1-y) As, thus forming an n-type channel. Conversely, for ap-channel transistor, if a highly negative voltage is applied to itsgate, i.e. a voltage lower than a threshold voltage V_(Tp), holes willaccumulate in the layer 5 of Ga_(y) In_(1-y) As, thus forming a p-typechannel.

FUNDAMENTAL PRINCIPLES OF THE INVENTION

In such structures, the threshold voltages V_(Tn) and V_(Tp) are givenby the following equations:

    V.sub.Tn =Φ.sub.Bn -ΔE.sub.c -A'.Q.d-c           (1)

    V.sub.Tp =-Φ.sub.Bp -ΔE.sub.v -A'.Q.d+c

Φ_(Bn) and Φ_(Bp) designate the heights of the Schottky barriersrelative to electrons and to holes, respectively;

ΔE_(c) and ΔE_(v) designate the discontinuity of the conduction band andof the valence band respectively between Al_(x) Ga_(1-x) As and Ga_(y)In_(1-y) As;

A' is a constant;

Q is the charge of the doping 3;

d is the distance between the Schottky gate and the layer 5; and

c is a constant depending on the geometry of the transistor.

In such structures, the threshold voltages V_(Tn) and V_(Tp) thus dependboth on the concentration of dopant and on the total thickness of thelayers 6 and 7, and their values are related by the equation:

    V.sub.Tn -V.sub.Tp =E.sub.g (Ga.sub.y In.sub.1-y As)       (2)

where E_(g) (Ga_(y) In_(1-y) As) designates the width of the forbiddenband of the layer 5 of Ga_(y) In_(1-y) As.

For reasons of symmetry, for a given thickness of the layers 5 and 6,the doping levels are often adjusted so that:

    V.sub.Tn =|V.sub.Tp |≈0.55 V

Although said value is quite acceptable for making complementaryintegrated circuits, it is known that it nevertheless leads to highelectrical power consumption since such electrical power consumptionincreases directly with said voltage. It is therefore highly desirableto reduce the threshold voltages to values close to 0.3 V or even lessif such values can be achieved.

With complementary metal-oxide semiconductor (CMOS) technology, as withsilicon technology, the threshold voltages of n-channel and p-channeltransistors are controlled independently by adjusting the concentrationof dopant for each type of transistor. Such adjustment is easilyperformed by using appropriate concentrations when implanting impuritiesindependently in the n-channel and in the p-channel. This solution mayalso be used with a HIGFET, as shown by G. S. LaRue and D .E. Grider inComplementary HFET 32-Bit Serial Multiplier, GaAs IC Symposium 1992Digest, p. 89.

This solution, which enables V_(Tn) and V_(Tp) to be reducedindependently, and which therefore enables the electrical powerconsumption of the integrated circuit to be reduced, has no effect onthe transconductance of the p-channel transistor. Unfortunately, it isknown that said transconductance is relatively low.

First Embodiment of the Invention

In a first embodiment of the invention, it is possible to provide asolution that improves the transconductance of the p-channel transistor(said first solution nevertheless having little effect on the thresholdvoltages V_(Tn) and V_(Tp)).

For the FIG. 1 structure described above, FIGS. 2a, 2b, and 2c show thecorresponding configuration of the conduction band E_(c) and of thevalence band E_(v), respectively at rest, with a positive gate voltage(thus corresponding to an n-channel transistor), and with a negativegate voltage (thus corresponding to a p-channel transistor). V_(G)represents the applied gate voltage (zero, positive, or negative, asappropriate), and E_(F) represents the Fermi level. Reference 10specifies the location at which electrons accumulate in an n-channeltransistor while reference 11 indicates the location at which holesaccumulate in a p-channel transistor.

It will be shown that the respective conduction conditions applicable toholes and to electrons are very different, which, in structures thathave been made in the past, gives rise to a very large mismatch betweenthe properties of n-channel transistors and the properties of p-channeltransistors integrated in the same circuit.

In GaAs or GaInAs it is known that electrons have a low effective massm*_(e), whereas holes have a high effective mass m*_(h) (it beingrecalled that "effective" mass corresponds to a statistical mean); inother words, the mobility of electrons is high whereas the mobility ofholes is low.

To remedy this drawback that prevents high-speed complementary logiccircuits being fabricated, proposals have been made by G. C. Osbourn etal. in Electron and Hole Effective Masses for Two-Dimensional Transportin Strained-Layer Superlattices, Superlattices and Microstructures, Vol.1, No. 3, p. 223 (1985) , to associate GaInAs with GaAs or AlGaAs inorder to establish a strained layer of GaInAs which has the effect ofreducing the effective mass of holes by means of physical phenomena thatare complex and that are explained briefly below.

In an unstrained material, the valence band of GaAs or GaInAs is splitinto two bands of quite clearly separate curvatures. FIG. 3 is a graphin the {ξ, κ}plane (energy as a function of wave vector) showing thevalence band in this case: one of the bands, referenced HH is called the"heavy hole band" while the other band referenced LH is called the"light hole" band. It is known that the effective mass of holes isinversely proportional to the curvature of the band, as given by thefollowing equation:

    m*.sub.h =-h.sup.2 /(∂.sup.2 ξ/∂κ.sup.2)(3)

where -h is Planck's constant, ξ is energy and κ is the wave vector.

If a strained material is now considered, e.g. a thin layer of GaInAssandwiched between two layers of GaAs or of AlGaAs (as shown in FIG. 4),the GaInAs layer is subjected to compression in the plane parallel tothe interface as represented by arrows 12, whereas the same layer issubjected to tension in the perpendicular plane as represented by arrow13.

In the corresponding valence band diagram, shown in FIG. 5, the effectof the above deformations is to separate the valence bands and to deformthem considerably in the plane parallel to the interface.

In FIG. 5, the righthand half-plane corresponds to the wave vectorκ.sub.∫ parallel to the interface while the lefthand half-plane showsthe wave vector κ⊥ perpendicular to the interface. Parallel to theinterface (i.e. for the right hand half-plane in the diagram of FIG.5),the bands are highly deformed, with "heavy" holes HH becoming light andconversely with "light" holes LH becoming heavy, whereas perpendicularlyto the interface (i.e. in the lefthand half-plane of FIG. 5), "heavy"holes HH remain heavy and "light" holes LH remain light. In other words,the light/heavy character of holes has been swapped over in one of thevalence bands but not in the other.

The deformation of these valence bands also changes the statisticaldistribution of the hole populations: thus, on average, in aGaAs/GaInAs/GaAs system or in an AlGaAs/GaInAs/AlGaAs system theeffective mass of the holes is less than in a non-strained GaAs/AlGaAssystem. Thus, in such a strained system p-channel transistors presentincreased mobility, and as a result better transconductance g_(mp). Theabove-mentioned work of Grider thus mentions transconductances g_(mp)reaching 70 mS/mm (millisiemens per millimeter) for transistors having agate of length 1 μm. Nevertheless, that value is much lower than thecorresponding values g_(mn) of the transconductances of n-channeltransistors which are of the order of 300 mS/mm, giving a ratio of 4.3that still needs to be overcome if it is desired that the p-channeltransistor should operate as well as the n-channel transistor.

The invention seeks to overcome this limitation by combining the variousphysical effects that take place in the thin layer 5 of Ga_(y) In_(1-y)As (effect of mechanical strain on the band diagram, quantum effect onthe energy position of the holes) and on the physical effects that placein the layer 6 of Al_(x) Ga_(1-x) As (tunnel effect), so as to increasethe transconductance of the p-channel transistor and thus enable it tooperate with higher performance.

Initially we consider these physical effects in a symmetrical structurecomprising a layer 4 of Al_(x) Ga_(1-x) As (instead of GaAs), a layer 5of Ga_(y) In_(1-y) As, and a layer 6 of Al_(x) Ga_(1-x) As; subsequentlywe consider the case where the layer 4 is a layer of GaAs.

It has been shown, in particular as described in French patentapplication 91-15140 in the name of the Applicant, that the tunnelingeffect of electrons through the layer 6 of Al_(x) Ga_(1-x) As needs tobe minimized in order to reduce gate leakage current.

FIGS. 6a and 6b show the appearance of the valence band E_(v) of saidAl_(x) Ga_(1-x) As/Ga_(y) In_(1-y) As/Al Ga₁ As stack of layers (layers4, 5, and 6) respectively at equilibrium and under negative gate bias.Potential barriers correspond to the layers of Al_(x) Ga_(1-x) As,whereas a quantum well corresponds to the layer of Ga_(y) In_(1-y) As.Within this quantum well, there appear sub-bands HH₁, HH₂, HH₃, . . . ,and LH₁, LH₂, . . . , respectively occupied by "heavy" holes and by"light" holes, i.e. holes that would be respectively heavy or light inGa_(y) In_(1-y) As in the non-strained state. As mentioned above, theseterms do not prejudice the genuinely heavy or light character of theholes since that property depends on the direction (parallel orperpendicular to the plane of the layers) in which hole motion isconsidered.

In the context of the invention, the only motion that is of interest isperpendicular to the plane of the layers, i.e. the effect of holestunneling through the barrier constituted by the layer 6 of Al_(x)Ga_(1-x) As. The effective mass of holes in this direction is writtenm*_(h)⊥.

It has been shown by P. Ruden et al., in Quantum Well p-ChannelAlGaAs/InGaAs/GaAs Heterostructure Insulated-Gate Field-EffectTransistors, IEEE Transactions on Electron Devices, Vol. 36, No. 11, p.2371 (1989) that LH holes have an effective mass m*_(h)⊥ of the order of0.07 m_(O), where m_(O) is the electron mass. Such a value which is veryclose to the corresponding value for electrons in Ga_(y) In_(1-y) As, isabout 5.5 times smaller than the value corresponding to HH holes.

Under high negative gate bias, the hole tunnel effect takes placeessentially only with LH holes, given that tunneling probability Tincreases with decreasing effective mass, in accordance with thefollowing equation:

    T=A exp-{ m.sup.*1/2 ΔE.sup.3/2 d)!/V}               (4)

A being a constant;

m* being the effective mass of electrons or of holes, as appropriate;

ΔE being the height of the potential barrier;

V being the applied voltage; and

d being the thickness of the layer 6 of Al_(x) Ga_(1-x) As.

FIG. 6b is a diagram of such a situation. If reference is made to thework by B. Laikhtman et al., Strained Quantum Well Valence-BandStructure and Optimal Parameters for AlGaAs-InGaAs-AlGaAs p-ChannelField-Effect Transistors, J. Appl. Phys., Vol. 70, No; 3, p. 1531 (1991)or by I .J. Fritz et al., in Appl. Phys. Lett., Vol. 48, p. 1678 (1968),the LH₁ and LH₂ sub-bands move rapidly towards high energies withincreasing concentration of indium in the layer 5 of Ga_(y) In_(1-y) As.When the indium content exceeds 20%, LH₁ is at least about 150 mV fromHH₁. For such a difference in energy position, the hole density in theLH₁ sub-band is less than a few hundredths of the hole density in theHH₁ sub-band. With 25% indium, the density ratio is no more than a fewthousandths. Thus, if an indium content of more than 25% is chosen, thetunneling effect due to holes occupying the LH₁ and LH₂ sub-bands can beignored.

We now consider the tunnel effect due to the holes occupying the HH₁,HH₂, . . . sub-bands and we compare them with the effect due toelectrons in the n-channel transistor.

The effective mass m*_(e) of an electron in the n-channel is of theorder of 0.07 m_(O). For a given thickness of the layer 6 of Al_(x)Ga_(1-x) As, the tunneling effect due to electrons is greater than thatdue to holes in sub-levels HH₁ and HH₂ which, it is recalled, have aneffective mass m*_(h)⊥ of the order of 0.4 m_(O), as given by Equation(4). Equation (4) also shows that the tunneling probability is afunction of the barrier width ΔE, i.e. of ΔE_(c) (the conduction banddiscontinuity between Al_(x) Ga_(1-x) As of the layer 6 and Ga_(y)In_(1-y) As of the layer 5) for electrons and ΔE_(v) (the discontinuityin the valence band) for HH₁ and HH₂ holes.

If reference is made to the work of J. Batey et al., Energy BandAlignment in GaAs: (Al,Ga)As Heterostructures: The Dependence on AlloyComposition, J. Appl. Phys., Vol. 59, No. 1, p. 200 (1986) and to thework of R .A. Kiehl et al., Parallel and Perpendicular Hole Transport inHeterostructures with high AlAs Mole-Fraction Barriers, Appl. Phys.Lett., Vol. 58, No. 9, p. 954 (1991), it can be deduced for the alloycomposition ranges under consideration herein, that the followingbarrier width values apply for an aluminum concentration x_(Al) ≈0.75:ΔE_(c) =800 mV and ΔE_(v) =520 mV Equation (4) then shows that to obtainthe same leakage current due to the tunneling effect, the p-channeltransistor can tolerate a thickness e_(p) of Al_(x) Ga_(1-x) As that issmaller than the thickness e_(n) for the n-channel transistor, with saiddifference giving rise to a ratio e_(n) /e_(p) =1.25.

We now consider the case where the quantum well is not symmetrical (thecase described by Grider in the article mentioned above), and whichcorresponds to a structure in which the layers 4, 5, and 6 arerespectively GaAs, Ga_(y) In_(1-y) As, and Al_(x) Ga_(1-x) As.

The valence band diagram for this structure is given in FIGS. 7a and 7b,respectively at rest and under a negative gate voltage. Twodiscontinuities can be seen in the valence band, namely ΔE_(v1) betweenthe layer 6 of Al_(x) Ga_(1-x) As and the layer 5 of Ga_(y) In_(1-y) As,and ΔE_(v2) between the layer 4 of GaAs and the layer 5 of Ga_(y)In_(1-y) As. It may be observed that ΔE_(v2) is small, of the order of100 mV, so that the LH₁ level is situated in the continuous spectrum.However, this situation changes rapidly under negative bias of the gatesince, under such circumstances, a pseudo-triangular quantum well (FIG.7b) is formed in this case and the LH₁ level appears in the well, in amanner that is comparable to the symmetrical quantum well in FIGS. 6aand 6b, which situation is described above.

The conclusions are thus essentially the same in both cases, and inparticular that to obtain the same tunneling effect leakage current inboth complementary transistors, the p-channel transistor must have athickness of Al_(x) Ga_(1-x) As that is less than the thicknesses of then-channel transistor, with the ratio of said thicknesses being of theorder of 1.25.

We now consider the practical problem which consists in making p-channeltransistors on the same substrate as n-channel transistors in spite ofhaving a thinner layer 6 of Al_(x) Ga_(1-x) As.

By way of example, if the layer 6 of Al_(x) Ga_(1-x) As of the n-channeltransistor has a thickness e_(n) =25 nm, then the thickness of thep-channel transistor should be e_(p) =20 nm. Such layers are extremelythin and thickness control must be as accurate as possible in order tooptimize the transconductances and the leakage currents of thetransistors.

To this end, the invention proposes a method of manufacture that impliesmodifying the epitaxial structure of the layer 6 compared with thestarting structure of FIG. 1.

FIG. 8 shows the novel epitaxial structure: on layers 1 to 5 made in thesame manner as the layers in FIG. 1, the layer 6 of Al_(x) Ga_(1-x) Asis replaced with a set of three successive layers comprising a firstlayer 15 of Al_(x) Ga_(1-x) As (having an aluminum content x_(Al) of notless than 0.70) of thickness 20 nm, a layer 16 of GaAs that is about 1nm thick, and finally a layer 17 of Al_(x) Ga_(1-x) As that is 5 nmthick. It will be observed that the sum of the thicknesses of the layers15 and 17 (20 nm+5 nm) is equal to the thickness of the equivalent layer6 in the FIG. 1 structure, i.e. 25 nm, and that the ratio of the totalthickness (layer 15+layer 17) relative to the layer 15 on its own isequal to (20+5)/20=1.25, i.e. the above-mentioned predeterminedthickness ratio. If the thickness of the layer 6 in the startingstructure is not 25 nm, but has some other value, then the thicknessesof the layers 15 and 17 should be modified accordingly.

The n-channel transistor will make use of a gate deposited on thesurface layer 7 of GaAs (as in FIG. 1), whereas the p-channel transistorwill make use of a gate deposited on the layer 16 (and not on the layer7).

To this end, special etching is performed that consists, after making asurface deposit of a layer of photosensitive resin 18, initially inopening a location 19 in said layer, at the bottom of which the gate G'of the p-channel transistor is to be deposited; this first etchingoperation is performed chemically, by ion milling, or with reactive ionetching, and it may continue in part into the layer 17 down to the levelreferenced 20 in FIG. 8. In the opening formed in this way, the layer 17is then selectively dissolved so that etching comes to an end veryaccurately at the level of layer 16 (level referenced 21 in FIG. 8).This final selective etching may be simply performed chemically usingdilute hydrofluoric or hydrochloric acid, which is known to haveselectivity that exceeds 10⁵.

It is then possible to deposit metal to constitute the gate G', as shownin FIG. 9. The gate electrode G of the n-channel transistor (lefthandhalf of the figure) is deposited directly on the surface layer 7, whilethe gate electrode G' of the p-channel transistor (righthand half of thefigure) is deposited on the deep layer 16 of GaAs at the bottom of theopening provided in the preceding step. The various drain and sourceelectrodes D, D', S, S' are deposited on the surface layer 7.

Second Embodiment of the Invention

As mentioned above, the first embodiment of the invention serves toimprove the transconductance of the p-channel transistor, but it haslittle effect on the threshold voltages V_(Tn) and V_(Tp). As alsomentioned, these voltages have a considerable effect on the electricalpower consumption of the circuit, so it is appropriate to furtherimprove the structure of the invention by means of a technique thatserves simultaneously to adjust the threshold voltages V_(Tn) and V_(Tp)independently and to increase the transconductance of the p-channeltransistor.

The second embodiment of the present invention seeks to achieve thisresult.

The initial structure is similar to that of FIGS. 8 and 9. However, thethicknesses of the layers 15 and 17, and the doping 3 are chosen in sucha manner as to reduce the threshold voltages of the transistorssimultaneously to values below 0.55 V (for the threshold voltage of thep-channel transistor, it is the absolute value |V_(Tp) | that is takeninto account not the algebraic value V_(Tp)). To determine an order ofmagnitude, if the overall thickness of the layers 7, 15, 16, and 17 is28 nm, and if the doping 3 is at 5×10¹¹ cm⁻², then the threshold voltageof the n-channel transistor will be about 0.45 V.

If the gate of the p-channel transistor is deposited on the layer 7 asis done conventionally in the prior art (see FIG. 1), then the thresholdvoltage V_(Tp) of the p-channel transistor is of the order of -0.65 V,which is too large (in absolute value).

The structure of the invention makes it possible to deposit the gate ofthe p-channel transistor on the layer 16, possibly by using a techniquedescribed above with reference to the first embodiment of the invention.This gate is closer to the layer 5 than is the gate of the n-channeltransistor. The threshold voltage |V_(Tp) | of the p-channel transistoris thus reduced (in absolute value). By selecting an appropriate valueof thickness for the layer 15, it is thus possible to adjust thethreshold voltage V_(Tp) of the p-channel transistor, with the doping 3being predetermined as described above. To determine an order ofmagnitude, with doping at 5×10¹¹ cm⁻², the thickness of the layer 15must be of the order of about 15 nm to ensure that the threshold voltageV_(Tp) is of the order of -0.45 V.

Relative to the overall thickness of the layers 7, 15, 16, and 17, whichis equivalent to the thickness of the layers 6 and 7 in the prior art,the thickness of the layers 15 and 16 is smaller by a factor equal toabout 1.7. Given that the transconductance of a HIGFET is proportionalto the distance between its gate and the channel which constitutes thelayer 5, the structure of the invention can therefore improve thetransconductance of the p-channel transistor by a factor of 1.7.

As explained above, the effective masses of holes in the transversedirection are greater than the effective masses of electrons, such thatthe gate-channel distance of the p-channel transistor can be reducedwithout the gate leakage current due to the tunnel effect becoming toohigh. In this approach, a reduction in thickness by a factor of about1.25 has been observed. However this factor may be greater than that. Inthe first embodiment of the invention described above, it is assumedthat the gate leakage current of the n-channel transistor is due to thecurrent tunneling through the potential barrier defined by ΔE_(c), withthe Γ conduction band being taken as the band that determines the tunneleffect. However, under certain conditions, in particular when thethickness of the barrier is greater than about 10 nanometers, the tunneleffect is assisted by the X band. Under such circumstances, above x_(Al)=0.45, the width of the barrier ΔE_(c) varies slightly with aluminumconcentration: between x_(Al) =0.45 and x_(Al) =1, ΔE_(c) varies fromabout 500 meV to about 550 meV. By using the same calculations as thoseexplained above for the first embodiment of the invention, it is foundthat the thickness of the layer 15 can be reduced by a factor of 2relative to the thickness of the layer 17.

Returning to the example given above, the layer 15 thus has a thicknessof 12.5 nm, which suffices for bringing the threshold voltage V_(Tp) toabout -0.43 V.

In accordance with the invention, a further improvement can be providedto the stack of layers 15 and 17 that enables the leakage current of thep-channel transistor gate to be reduced while still further reducing thethickness of the set of layers 15 and 16. The gate leakage current ofthe p-channel transistor depends mainly on two parameters that relate tothe material of the layer 15: its thickness and its composition, whichparameters define the height of the potential barrier ΔE_(v), i.e. thevalence band discontinuity between the material Ga_(y) In_(1-y) As oflayer 5 and the material of layer 15. Heretofore, the material of layer15 has been chosen to be identical with that of layer 17, i.e. Al_(x)Ga_(1-x) As with x_(Al) close to 0.75. However it is much moreadvantageous to increase the concentration x_(Al) of the layer 15 inorder to increase the width of the potential barrier ΔE_(c), therebyreducing the gate leakage current. It is quite possible to envisageincreasing x_(Al) up to 1, in other words having a layer 15 that is madeof AlAs. Calculations based on the effect of holes tunneling through thepotential barrier ΔE_(v) show that increasing x_(Al) from 0.75 to 1makes it possible to reduce the gate leakage current by a factor ofabout 6. Given that tunneling probability is given by above-specifiedEquation (4), it is easy to deduce that increasing ΔE_(v) makes itpossible to reduce d (the thickness of layer 15) while keeping the sametunnel probability, i.e. the same leakage current. Increasing x_(Al)from 0.75 to 1 thus makes it possible to reduce the thickness d of thelayer 15 by a factor of about 1.4.

Thus, starting from a nominal thickness of 28 nm for the set of layers7, 15, 16, and 17, it is possible to apply successive thicknessreductions by a factor 2 due to the difference in effective masses ofholes and electrons, and then by a factor of 1.4 due to the use of AlAsinstead of Al_(x) Ga_(1-x) As. The total improvement is thus by a factorof 2×1.4=2.8, thereby enabling a thickness of the layer 15 to be reducedto 9 nm. The threshold voltage |V_(Tp) | will thus decrease by about0.05 V, bringing it down to 0.37 V. This reduction in the thresholdvoltage is accompanied by an increase in transconductance by a factor ofabout 2.8.

So far, 5×10¹¹ cm⁻² has been taken as an example of the value for thedoping 3, but it will be understood that the effects of reducing thethreshold voltage and of increasing the transconductance as explainedabove are equally applicable to doping at other values. Thus, the doping3 need not necessarily be performed uniformly, but may be performed byimplanting electron donor impurities locally in the channels of n-typetransistors, while avoiding any intentional doping of p-channeltransistors.

Doing this makes it possible to further reduce the threshold voltage|V_(Tp) | of the p-channel transistor down to a value close to 0.10 V to0.15 V. By adjusting the localized doping of n-channel transistors, itis also possible to adjust the voltage V_(Tn) to similar values.Complementary transistors are thus obtained, both of which operate atvery low threshold voltages, which constitutes an improvement over theresults published by G. S. LaRue and D. E. Grider in Complementary HFET32-Bit Serial Multiplier, GaAs IC Symposium 1992 Digest, p. 89, wherethe p-channel transistor had its threshold voltage fixed at -0.34 V. Theother advantage is clearly the improvement in the transconductance ofthe p-channel transistor.

In an even more elaborate technique, it is also possible to adjust thethreshold voltages of the n-channel and the p-channel transistorsindependently by implanting impurities in localized manner both in thechannels of n-channel transistors and in the channels of p-channeltransistors, by choosing different implanting concentrations for the twotypes of transistor or by implanting electron donor impurities in then-channel transistors while implanting hole donor impurities (also knownas acceptors) in the p-channel transistors.

Until now, attempts have been made to optimize the composition of thelayer 15 without worrying about technological problems relating to themanufacture of transistors.

Unfortunately, it is known that an aluminum-rich Al_(x) Ga_(1-x) Asalloy, and thus a fortiori an alloy of AlAs, gives rise to difficultiesin implementing the source and drain ohmic contacts, thus having theeffect of creating high access resistances that hinder good operation ofthe transistors, and more particularly of n-channel transistors (see forexample the above-specified article by A. I. Akiwande et al.).

To prevent the highly aluminum-rich layer 15 degrading accessresistances to the n-channel transistor, it is possible to reduce thealuminum concentration in the layer 17 so that the mean concentration ofthe layers 15+17 remains equal to 0.75, which implies that the aluminumconcentration in the layer 17 should have a value of about 0.5 to about0.6. A. I. Akiwande et al. have shown in the above-mentioned articlethat the gate leakage current of the n-channel transistor does notimprove much beyond a concentration of 0.6, thus making it possible tohave a good compromise between low gate leakage current and ease ofimplementing ohmic contacts.

In this context of facilitating implementation of ohmic contacts byusing materials having low aluminum content, it is possible to replacethe Al_(x) Ga_(1-x) As of the layers 15 and 17 with Al_(u) In_(1-u) P(with u_(Al) ≈0.4) or with (Al_(x) Ga_(1-x))_(u) In_(1-u) P in which theconcentration x_(Al) is close to 1, thereby increasing the heights ofthe potential barriers ΔE_(c) and ΔE_(c). According to S. Tiwari and D.F. Frank in Empirical Fit to Band Discontinuities and Barrier Height inIII-V Alloy Systems, Applied Physics Letters, 60, No. 3, 630 (1992), thecompound Al_(u) In_(1-u) P has potential barriers ΔE_(c) and ΔE_(v) ofwidths greater than those of AlAs. From this point of view it istherefore more favorable than Al_(x) Ga_(1-x) As.

According to the invention, it is possible in even more general mannerto adopt III-V semiconductor materials of entirely differentcompositions for the layers 15, 16, 17, and 7 in order to give each ofthem its own particular properties.

A first example concerns the layer 7 and/or the layer 16. Until now,this has been of GaAs material which provides a protective functionagainst oxidation at the surface of the Al_(x) Ga_(1-x) As. As explainedabove with respect to the first embodiment of the invention, it alsoacts as a selectivity agent for chemical etching, thus facilitating themethod of manufacturing the integrated circuit.

However, its role in reducing the gate leakage current due to the tunneleffect is zero. Worse, its presence increases the thickness of the setof layers and thus it increases the threshold voltage and decreases thetransconductance. When layers are used that are about 25 nm thick, anexcess of thickness of 3 nm due to the layer 7 may in the limit, beconsidered as negligible, however, when the thickness is reduced to 10nm as explained above for the layer 15, a value of 3 nm is no longernegligible. Under such circumstances, it is desirable to use a III-Vsemiconductor material having a wider forbidden band that is not subjectto excessive surface oxidation and that has a lattice constant thatmatches that of the substrate or that has only a small mismatchtherewith. A small mismatch in the lattice constant of the layer 16relative to the substrate may be in compression or in extension. If itis compression, then the mechanical tension adds to that of the layer 5,and it is necessary for the set of mechanical tensions in the layers 5and 16 not to exceed a critical value, since otherwise dislocations willappear at the interfaces. One such wide forbidden band material isAlGaAs with a low aluminum content. However it is advantageous to use amaterial that does not contain an easily oxidized element such asaluminum. Ga_(u) In_(1-u) P (u_(Ga) =0.49) may be such a material, whichalso has the advantage of presenting a wide potential barrier ΔE_(v),relative to III-V compounds based on arsenic (see, for example, theabove-mentioned article by S. Tiwari and D. J. Frank, or else an articleby J. O. McCaldin and T. C. Gill, Comment on Empirical Fit to BandDiscontinuities and Barrier Heights in III-V Alloy Systems, AppliedPhysics Letters, 61, No. 18, 2243 (1992)).

In addition, Ga_(u) In_(1-u) P also has the advantage of a low rate ofchemical etching by the dilute acids used for digging into the layer 15,as described above with respect to the first embodiment of theinvention.

Remaining in the context of choosing different materials, two differentmaterials may be considered for use in the layers 15 and 17 in order tooptimize the main parameters that determine the threshold voltage andthe gate leakage current in a manner that is separate for p-channeltransistors and for n-channel transistors.

Consider initially the leakage current parameter. It is recalled that itdepends on the heights of the potential barriers ΔE_(c) and ΔE_(v). Ifthe layers 15 and 17 are of the same kind, then ΔE_(c) and ΔE_(v) arerelated by the equation ΔE_(c) +ΔE_(v) =ΔE_(g), where ΔE_(g) designatesthe difference between the forbidden band energies of the material inlayers 15 and 17 and the material in layer 5.

If different materials are selected for the layers 15 and 17, a targetcan be established to find a material having wide ΔE_(v) for the layer15 and a material having wide ΔE_(c) for the layer 17.

Thus, for expitaxial growth on a GaAs substrate, the material for thelayer 15 may be AlAs or Al_(u) In_(1-u) P (u_(Al) ≈0.49) which have awide ΔE_(v) barrier, while the material for the layer 17 may be GaP_(s)Sb_(1-s) (s_(P) ≈0.65) which has a wider ΔE_(c) barrier than AlAs orAl_(u) In_(1-u) P (whereas its ΔE_(v) barrier is very narrow, beingclose to zero; see for example FIG. 1 of the above-mentioned article byS. Tiwari and D. J. Frank).

For epitaxial growth on InP, the layer 5 which is under mechanicalstrain, may be Ga_(y) In_(1-y) As with Y_(Ga) being of the order of 0.12to 0.27, whereas the material having a wide forbidden band and matchingthe lattice constant of the substrate may be InP, Al_(z) In_(1-z) As(z_(Al) ≈0.4), or else GaP_(s') Sb_(1-s') (with s'_(P) ≈0.35). However,in that system, it is clear that Al_(z) In_(1-z) As has a ΔE_(v) barrierthat is not wide enough (about 250 meV) to be effective. In contrast itsΔE_(c) barrier of about 500 meV is acceptable. Conversely, InP has aΔE_(v) width of about 500 meV and a ΔE_(c) width of about 250 meV. It isthus quite appropriate to use InP for the layer 15 and Al_(z) In_(1-z)As for the layer 17. With respect to the alloy GaP_(s') Sb_(1-s')(s'_(P) ≈0.35), the discontinuity of the valence band ΔE_(v) isnegative, so that there is no potential barrier. This compound thereforecannot be used in the layer 15. When used in the layer 17, it presents aΔE_(c) barrier of about 800 meV to electrons, which is very favorable.

The use of layers 15 and 17 of different kinds has an additionaladvantage of selectivity in chemical etching that makes it possible toremove the layer 15 without digging into the layer 17. In this case, theintermediate layer 16 becomes superfluous, thus making it possible tofurther reduce the absolute value of the threshold voltage |V_(Tp) | andto increase the transconductance of the p-channel transistor. In theexample mentioned above where the layer 15 is reduced to 10 nm, if the 3nm layer 16 is removed, transconductance is improved by 30% and V_(Tp)is improved by 0.03 V, i.e. by about 10%.

In addition, by using different materials for the layers 15 and 17 so asto increase the values of ΔE_(c) and ΔE_(v), it is tempting to believethat in the light of equation (1) the threshold voltages V_(Tn) and|V_(Tp) | will increase pro rata the increases in ΔE_(c) and ΔE_(v).Unfortunately, Φ_(Bn) and Φ_(Bp) are magnitudes that also depend on thematerials used. From FIG. 1 in the above-mentioned article by S. Tiwariand D. J. Frank, it is clear that the differences (Φ_(Bn) -ΔE_(c)) and(-Φ_(Bn) +ΔE_(v)) are zero to a first approximation.

In addition, all of these considerations concerning threshold voltage,transconductance, or gate leakage current have little connection withthe quantum phenomena already described in related French patentapplications 92-00668 and 92-08985 in the name of the Applicant. Thethickness of the layer 5 can thus have a value that is close to 6 nm to8 nm, and between the layer 5 and the buffer layer 2, it may optionallybe possible to interpose a layer 22 (FIG. 9) presenting relative to thelayer 5 a valence band discontinuity of about 100 meV or more, so as toprovide better separation between the HH₃ sub-band and the othersubbands HH₁ and HH₂.

I claim:
 1. An integrated circuit having complementary components of thep-channel and n-channel field effect transistor type, with aheterojunction formed between a barrier layer comprising a III-Vsemiconductor material having a wide forbidden band and a thin layercomprising a III-V semiconductor material having a narrow forbidden bandand whose crystal lattice mismatch with the remainder of the structureis such that the thin layer is under uniaxial compression strain in theplane of the layer, wherein the barrier-layer thickness for thep-channel transistor is less than the barrier-layer thickness for then-channel transistor at a ratio that is proportional to tunnelingprobability for holes compared with that for electrons through thebarrier layer, in a direction perpendicular to the plane of the barrierlayer and thin layer interface.
 2. The integrated circuit of claim 1wherein the heterojunction defines a quantum well including heavy hole,HH, and light hole, LH, type sub-bands in the valance-band diagram ofthe heterostructure in the level that comprises the narrow forbiddenband, and wherein the material comprising the narrow forbidden bandeffects energy differences among the sub-bands HH₁, HH₂ and LH₁, suchthat the LH₁ sub-band population is, essentially, negligible, and then-channel transistor gate-leakage current is, essentially, independentof tunneling probability for heavy holes HH₁ and HH₂.
 3. The integratedcircuit of claim 1 wherein the thickness ratio of the layer reduces theabsolute values of threshold voltages of said transistors, therebyreducing the electrical power consumption of the circuit whileincreasing the transconductance of the p-channel transistor.
 4. Theintegrated circuit of claim 1, in which the wide forbidden band materialis AlGaAs and the narrow forbidden band material is GaInAs, saidmaterials being grown epitaxially on a substrate of GaAs.
 5. Theintegrated circuit of claim 1, in which the wide forbidden band materialis (AlGa)InP and the narrow forbidden band material is GaInAs, saidmaterials being grown epitaxially on a substrate of GaAs.
 6. Theintegrated circuit of claim 1, in which the wide forbidden band materialis AlInAs and the narrow forbidden band material is GaInAs, saidmaterials being grown epitaxially on a substrate of InP.
 7. Theintegrated circuit of claim 1, in which the wide forbidden band materialis InP and the narrow forbidden band material is GaInAs, said materialsbeing grown epitaxially on a substrate of InP.
 8. The integrated circuitof claim 1, in which:the barrier layer includes an epitaxial stackcomprising:a first elementary layer comprising the wide forbidden bandmaterial;, a second elementary layer different in composition from thefirst elementary layer, and suitable for facilitating selective etchingthereof; and a third elementary layer comprising the wide forbidden bandmaterial; the ratio of the thickness of the first elementary layer tothe total thickness of the first and third elementary layers is equal tosaid tunneling probability ratio; andgate G' of the p-channel transistoris disposed to contact the second elementary layer.
 9. The integratedcircuit of claim 3, in which:the barrier layer includes an epitaxialstack comprising:a first elementary layer comprising the wide forbiddenband material; a second elementary layer different in composition fromthe first elementary layer, and suitable for facilitating selectiveetching thereof; and a third elementary layer comprising the wideforbidden band material; the ratio of the thickness of the firstelementary layer to the total thickness of the first and thirdelementary layers is equal to said tunneling probability ratio; and gateG' of the p-channel transistor is disposed to contact the secondelementary layer, in which the threshold voltages of the transistors, inabsolute terms, are less than 0.5 V.
 10. The integrated circuit of claim9, in which the transconductance of the p-channel transistor isincreased by a factor of more than 1.25 relative to that of a p-channeltransistor having its gate deposited on the barrier layer.
 11. Theintegrated circuit of claim 8, in which the composition of the firstelementary layer (a) effects a potential barrier ΔE_(v) corresponding tothe discontinuity in the valence band between the first elementary layerand the thin layer, (b) determines the tunneling probability for holes,(c) is independent of the potential barrier ΔE_(c) corresponding to theconduction band discontinuity between the material of the thirdelementary layer and of the thin layer, and (d) determines tunnelingprobability for electrons, thereby reducing the thickness of the firstelementary layer and consequently reducing the threshold voltages of thetransistors to values of less than about 0.4 v, and increasing thetransconductance of the p-channel transistor, relative to an integratedcircuit where the first and third elementary layers are identical. 12.The integrated circuit of claim 11, in which the first elementary layercomprises AlAs and the third elementary layer comprises Al_(x) Ga_(1-x)As, wherein 0.5≦x≦0.75, epitaxially grown on a GaAS substrate.
 13. Theintegrated circuit of claim 11, in which the first elementary layercomprises AlAs and the third elementary layer comprises Al_(u) In_(1-u)P, wherein u≈0.50, epitaxially grown on a GaAs substrate.
 14. Theintegrated circuit of claim 11, in which the first elementary layercomprises Al_(u) In_(1-u) P, wherein u≈0.50, and the third elementarylayer comprises Al_(x) Ga_(1-x) As, wherein 0.5≦x≦0.75, epitaxiallygrown on a GaAs substrate.
 15. The integrated circuit of claim 11, inwhich the first elementary layer comprises Al_(u) In_(1-u) P, whereinu≈0.50, and the third elementary layer comprises GaP_(s) Sb_(1-s),wherein s≈0.65, epitaxially grown on a GaAs substrate.
 16. Theintegrated circuit of claim 16, in which the first elementary layercomprises InP and the third elementary layer comprises Al_(z) In_(1-z)As, wherein z≈0.48, epitaxially grown on a InP substrate.
 17. Theintegrated circuit of claim 11, in which the first elementary layercomprises InP and the third elementary layer comprisesGaP_(s),Sb_(1-s'), wherein s'≈0.35, epitaxially grown on a InPsubstrate.
 18. The integrated circuit of claim 15, in which:the barrierlayer includes an epitaxial stack comprising:a first elementary layercomprising the wide forbidden band material; and a second elementarylayer comprising the wide forbidden band material; a third elementarylayer comprising the wide forbidden band material; the ratio of thethickness of the first elementary layer to the total thickness of thefirst and third elementary layers is equal to said tunneling probabilityratio; and gate G' of the p-channel transistor is disposed to contactthe second elementary layer; wherein-selective etching of the firstelementary layer is effected by the first elementary layer having adifferent composition than the third elementary layer.
 19. Theintegrated circuit of claim 1, wherein the n-channel transistor includesa doping material.
 20. The integrated circuit of claim 19, wherein thep-channel transistor includes no doping material.
 21. The integratedcircuit of claim 19, wherein the p-channel transistor includes a dopingmaterial at a concentration different from the concentration of thedoping material in the n-channel transistor.
 22. The integrated circuitof claim 1, further comprising a separation layer interposed between abuffer layer and the thin layer, presenting, relative to the thin layer,a valence band discontinuity that is not less than about 100 meV.